1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device capable of electrically rewriting data and semipermanently retaining data.
2. Description of the Related Art
Nonvolatile semiconductor memory devices using double-gate MOS transistors with a floating gate and a control gate are well known.
A conventional nonvolatile semiconductor memory device will be explained with reference to FIGS. 1 to 10.
FIGS. 1 and 2 show a first structure of a conventional nonvolatile semiconductor memory device.
The nonvolatile semiconductor memory device is of the most widely used type. FIG. 1 is a plan view of a memory cell in the nonvolatile semiconductor memory device. FIG. 2 is a sectional view taken along line II-II' of FIG. 1.
The memory cell is composed of a data storage MOS transistor MT and a select MOS transistor ST, which are connected to each other in series.
The source region of the select MOS transistor ST and the drain region of the data storage MOS transistor MT are made up of n-type regions 12 and 13 at the surface of a p-type semiconductor substrate 10, respectively.
On a partial surface of the n-type region, a very thin silicon oxide film 17 of nearly 10 nm in thickness is formed. A floating-gate electrode 19 and a control gate electrode 20 are formed on and above the channel region 22 of the data storage MOS transistor MT and the silicon oxide film 17. The floating-gate electrode 19 and control gate electrode 20 are made of polysilicon, for example.
In a place directly under the floating-gate electrode 19 where the silicon oxide film 17 has not been formed, and directly under the gate electrode 18 of the select MOS transistor ST, silicon oxide films 23, 16 (of several tens nm) several times as thick as the silicon oxide film 17 are formed.
The drain region of the select MOS transistor ST is composed of n-type regions 11, 12', and the source region of the data storage MOS transistor MT is made up of n-type regions 14, 15.
With the memory cell of such a configuration, the erasing of data is effected by applying a high potential to the control gate electrode 20 of the data storage MOS transistor MT. Specifically, once a high potential has been applied to the control gate electrode 20, Fowler-Nordheim tunneling allows electrons to move from the n-type region (drain region) 13 via the silicon oxide film 17 to the floating-gate electrode 19.
The writing of data is performed by applying a high potential to the n-type region (drain region) 11 and the gate electrode 18 of the select MOS transistor ST, and 0 V to the control gate electrode 20 of the data storage MOS transistor MT. As a result, the n-type regions (drain region) 12, 13 of the data storage MOS transistor MT are at a high potential, so that the tunnel effect allows electrons to move from the floating-gate electrode 19 to the drain region via the silicon oxide film 17.
Hereinafter, the source region and drain region of the memory cell will be described.
The n-type region (drain region) 13 of the data storage MOS transistor is formed directly under the floating-gate electrode 19 before the floating-gate electrode 19 is formed. On the other hand, the n-type region (source region) 15 of the data storage MOS transistor MT is formed in a self-aligning manner by implanting n-type impurities into the substrate 10 using the floating-gate electrode 19 and control gate electrode 20 as a mask.
when only the n-type region 15 is the source region, however, the channel length of the data storage MOS transistor MT is the distance between the n-type region 13 and the n-type region 15. Therefore, the channel length of the data storage MOS transistor MT varies depending on the misalignment of the mask for forming the n-type region 13 from the mask for forming a polysilicon mask used in forming the n-type region 15.
Since the change of the channel length of the data storage MOS transistor MT results in a change in the characteristics of the memory cell, it is not desirable to form only the source region in a self-aligning manner.
To avoid this problem, the following method is generally used: before the floating-gate electrode 19 is formed, n-type impurities are implanted into region D enclosed by a dot-dash line in FIG. 1, thereby forming the n-type region 13 and n-type region 14 at the same time.
with this method, the channel length of the data storage MOS transistor MT is the distance between the n-type region 13 and the n-type region 14. Since the n-type regions 13, 14 are formed with the same mask, the channel length of the data storage MOS transistor MT is always constant. As a result, the channel length of the data storage MOS transistor MT will not vary due to mask misalignment.
However, this method has a disadvantage in that, to assure the formation of the n-type region 14 directly under the floating-gate electrode 19, the floating-gate electrode 19 must be lengthened along the channel length of the data storage MOS transistor MT, by the sum of the amount of misalignment of the mask for forming the floating-gate electrode 19 and the amount of misalignment of the mask for forming the n-type regions 13, 14.
Hereinafter, the thin silicon oxide film 17 of nearly 10 nm in thickness between the n-type region 13 and the floating-gate electrode 19 will be examined.
The silicon oxide film 17 is formed by removing the thick silicon oxide films 16, 23 of several tens nm in thickness using a mask with an opening in area F in FIG. 1 and then performing thermal oxidation.
The thin silicon oxide film 17 must be formed on the n-type region 13 and directly under the floating-gate electrode 19. This causes a disadvantage: the floating-gate electrode 19 must be lengthened along the channel length by the sum of the amount of misalignment of the mask for forming the floating-gate electrode 19 from the mask for forming an opening in area F and the amount of misalignment of the mask for forming an opening in area F from the mask for forming the n-type region 13.
To sum up, the minimum dimension along the channel of the data storage MOS transistor MT in the memory cell is determined as shown in FIG. 3.
Specifically, the minimum dimension along the channel of the data storage MOS transistor MT is determined by the sum of the following:
The amount of alignment of the mask for forming the floating-gate electrode 19 and control electrode 20 from the mask for forming an opening in area F where the silicon oxide film 17 is to be formed (expressed by "a") PA1 The length of area F where the silicon oxide film 17 is to be formed (expressed by "b") PA1 The amount of misalignment of the mask for forming an opening in area F where the silicon oxide film 17 is to be formed from the mask for forming the n-type region 13 (expressed by "c") PA1 The channel length of the data storage MOS transistor MT (expressed by "d") PA1 The amount of misalignment of the mask for forming the n-type region 14 from the mask for forming the floating-gate electrode 19 and the control gate 20 (expressed by "e") PA1 The length of the second portion 40A of the floating-gate electrode (expressed by "a") PA1 The amount of misalignment of the mask for forming the n-type region 33 from the mask for forming the floating-gate electrodes 40A, 40B (expressed by "b" and "c") PA1 The channel length of the data storage MOS transistor MT (expressed by "d")
The memory cell of the structure shown in FIGS. 1 and 2 requires a lot of misalignments to be taken into account in designing, as compared with an ordinary MOS transistor having a self-aligning structure, and therefore has the disadvantage of resulting in larger memory cells.
Explained next will be the thickness of the gate oxide film of the data storage MOS transistor MT.
To withstand high voltages in a write operation or an erase operation, the gate oxide film of the select MOS transistor ST is several times as thick as the gate oxide film of a MOS transistor to which only an ordinary power-supply voltage (e.g., 5 V) is applied.
The gate oxide film of the data storage MOS transistor MT and the gate oxide film of the select MOS transistor ST are formed simultaneously. As a result, the gate oxide film of the data storage MOS transistor MT is as thick as the gate oxide film of the select MOS transistor ST.
To make the data storage MOS transistor MT smaller, it is necessary to make its gate oxide film as thin as possible. As mentioned above, the gate oxide film of the data storage MOS transistor MT is as thick as the gate oxide film of the select MOS transistor ST, that is, several times as thick as the gate oxide film of an ordinary MOS transistor. For this reason, the channel length of the data storage MOS transistor MT is larger than the channel length of an ordinary MOS transistor.
As described above, in the case of the memory cell shown in FIGS. 1 and 2, because a lot of misalignments have to be taken into account and a larger channel length is required, the cell area will become larger.
The potential of the floating gate when a high potential is applied to the drain region is determined by the capacitive coupling between the drain region and the floating gate. In the case of the memory cell of the above structure, the capacitive coupling between the drain region and the floating gate of the data storage MOS transistor MT varies according to the misalignment of the mask for forming the n-type region 13 from the mask for forming the floating-gate electrode 19. The variation in the capacitive coupling results in a variation in the amount of electrons released from the floating-gate electrode into-the drain region.
Accordingly, this causes variations in the threshold voltage of the data storage MOS transistor MT after electrons have been released.
FIGS. 4 and 5 show a double structure of a conventional nonvolatile semiconductor memory device. FIG. 4 is a plan view of a conventional nonvolatile semiconductor memory device. FIG. 5 is a sectional view taken along line V-V'.
The conventional nonvolatile semiconductor memory device has been disclosed in Jpn. Pat. Appln. KOKAI Publication No. 63-84168.
With this conventional device, it is possible to solve the problem with the conventional device shown in FIGS. 1 and 2, that is, it is possible to suppress variations in the write characteristics of the memory cell due to mask misalignment.
As with the conventional device of FIGS. 1 and 2, the memory cell is composed of a data storage MOS transistor MT and a select MOS transistor ST, which are connected to each other in series.
Above the channel region 39 of the data storage MOS transistor MT, a first portion 40B of a floating-gate electrode is provided via a gate insulating film 37 of several tens nm in thickness.
On a partial surface of the drain region 33 of the data storage MOS transistor MT, a gate insulating film 36 of nearly 10 nm in thickness (much thinner than the gate insulating film 37) is provided. On the gate insulating film 36, a second portion 40A of the floating-gate electrode is provided.
Although the first portion 40B and second portion 40A of the floating-gate electrode are spaced apart, they are electrically connected to each other above a field region. On and above the first portion 40B and second portion 40A of the floating-gate electrode, an insulating film 42 and a control gate electrode 44 are provided. It is preferable that the shape of the control gate electrode 44 should be the same as that of the floating-gate electrode.
The source region of the select MOS transistor ST and the drain region of the data storage MOS transistor are made up of n-type regions 32, 33, 34 formed continuously at the surface of a p-type semiconductor substrate 30. The drain region of the select MOS transistor ST is made up of n-type regions 31, 32', and an n-type region 35 is the source region of the data storage MOS transistor MT.
In such a memory cell, too, the n-type region 33 is formed before the formation of the floating-gate electrode and control gate electrode, as with the conventional device of FIGS. 1 and 2.
In this case, the n-type region 33 is formed by implanting n-type impurities into area E of the substrate 30 enclosed by a dot-dash line in FIG. 4. On the other hand, the n-type regions 32', 32, 34 are formed in a self-aligning manner by implanting n-type impurities into the substrate 30 using the floating-gate electrodes 40A, 40B and control gate electrode 44 as a mask. The n-type regions 31, 35 are formed by implanting n-type impurities into the substrate 30 using a specific mask.
With this conventional device, there arises a misalignment of the mask for forming the floating-gate electrodes 40A, 40B and a misalignment of the mask for forming the n-type region 33.
In the case of this conventional device, however, even if such mask misalignments take place, this will cause no variations in the capacitive coupling between the n-type regions (drain region) 32 to 34 of the data storage MOS transistor MT and the floating-gate electrodes 40A, 40B.
The reason for this is that the capacitive coupling between the n-type regions (drain region) 32 to 34 and the floating-gate electrodes 40A, 40B is determined by the area of the portion where the n-type region (drain region) 33 overlaps with the second portion 40A of the floating-gate electrode and the area is constant regardless of mask misalignment.
Consequently, with the memory cell in the conventional device, the write characteristics of the memory cell will not vary due to mask misalignment.
Furthermore, with the conventional device, the n-type regions 34, 35 can be formed in a self-aligning manner using the floating-gate electrodes 40A, 40B and control gate electrode 44 as a mask. Therefore, it is not necessary to take into account a misalignment of the mask for forming the n-type regions 34, 35 and a misalignment of the masks for forming the floating-gate electrodes 40A, 40B and control gate electrode 44.
To sum up, in the memory cell in the conventional memory cell, the minimum dimension along the channel length of the data storage MOS transistor MT is shown in FIG. 6.
Specifically, the minimum dimension along the channel length of the data storage MOS transistor MT is determined by the sum of the following:
However, when the minimum spacing (expressed by "e") in which the floating-gate electrode and control gate electrode (polysilicon) can be processed is greater than b+c, the minimum dimension is determined by a+d+e.
Hereinafter, the conventional device in FIGS. 1 and 2 is compared with the conventional device in FIGS. 4 and 5.
If a, b, c, and d in FIG. 3 are almost equal to c, a, b, and d in FIG. 6, the data storage MOS transistor MT of FIG. 6 can be made smaller by the length of e. As a result, with the conventional device of FIGS. 4 and 5, the dimensions of a memory cell can be made smaller than those of a memory cell in the conventional device of FIGS. 1 and 2.
However, in the memory cell in the conventional device of FIGS. 4 and 5, the thickness of the gate oxide film 37 of the data storage MOS transistor MT is larger. Accordingly, the channel length of the data storage MOS transistor MT is larger, so that the area of the memory cell cannot be made much smaller than that of the memory cell in the conventional device of FIGS. 1 and 2.
To overcome this shortcoming, a third structure of a conventional nonvolatile semiconductor memory device has been proposed in John R. Yeargain & Clinton Kuo, "A High Density Floating-Gate EEPROM Cell," IEDM Technical Digest, December, 1981.
FIG. 7 shows a third structure of a conventional nonvolatile semiconductor memory device. FIG. 8 is a sectional view taken along line VIII-VIII' of FIG. 7.
The memory cell is composed of a data storage MOS transistor MT and a select MOS transistor ST, which are connected to each other in series.
The source region of the select MOS transistor ST and the drain region of the data storage MOS transistor MT are composed of an n-type region 52 formed at the surface of a p-type semiconductor substrate 50. On the entire surface of the channel region 57 of the data storage MOS transistor MT, a thin silicon oxide film 54 of nearly 10 nm in thickness is formed. On the thin silicon oxide film 54, a floating-gate electrode 58 made of polysilicon is formed. On and above the floating-gate electrode 58, an insulating film 60 and a control gate electrode 61 are formed.
Directly under a gate electrode 59 of the select MOS transistor ST, an insulating film much thicker than the silicon oxide film 54, for example, a silicon oxide film 55 of nearly several tens nm in thickness, is formed.
The drain region of the select MOS transistor ST is composed of n-type regions 51, 52', and an n-type region 53 is the source region of the data storage MOS transistor MT.
With the memory cell of such a structure, the erasing of data is performed by applying a high potential to the control gate electrode 61 of the data storage MOS transistor MT. Once a high potential has been applied to the control gate electrode 61 of the data storage MOS transistor MT, Fowler-Nordheim tunneling allows electrons to move from the n-type region (drain region) 52, channel region 57, and n-type region (source region) 53 via the silicon oxide film 54 to the floating-gate electrode 58.
The writing of data is performed by applying a high potential to the n-type region (drain region) 51 and gate electrode 59 of the select MOS transistor ST, and 0 V to the control gate electrode 61 of the data storage MOS transistor MT. As a result, the n-type region (drain region) 52 of the data storage MOS transistor MT are at a high potential, so that the tunnel effect allows electrons to move from the floating-gate electrode 58 to the n-type region (drain region) 52 via the silicon oxide film 54.
with the structure of the memory cell, the n-type regions 52', 52, 53 are formed in a self-aligning manner using the gate electrode 59 of the select MOS transistor ST, the floating-gate electrode 58 and control gate 61 of the data storage MOS transistor MT as masks, respectively.
The thin silicon oxide film 54 is formed on the entire surface of the channel region of the data storage MOS transistor MT.
Therefore, unlike the conventional device of FIGS. 1 and 2 and that of FIGS. 4 and 5, it is not necessary to take into account the misalignment of the mask for forming the n-type regions 52', 52, 53 from the mask for forming the floating-gate electrode and the misalignment of the mask for specifying an area in which a silicon oxide film is to be formed from the mask for forming the floating-gate electrode.
Since the gate oxide film of the data storage MOS transistor MT is as thin as nearly 10 nm, the channel length can be made very small.
For the reasons described above, the area of the memory cell is much smaller than that in the conventional device of FIGS. 1 and 2 and that in the conventional device of FIGS. 4 and 5.
It is known that in a MOS device with a thin oxide film, a breakdown phenomenon takes place due to band-to-band tunneling. The phenomenon has been described in detail in R. Shirota, T. Endoh, M. Momodomi, R. Nakayama, S. Inoue, R. Kirisawa & F. Masuoka, "An Accurate Model of Subbreakdown due to Band-to-Band Tunneling and its Application," IEDM, 1988.
The phenomenon will be explained briefly.
For instance, with an n-channel MOS transistor, when a voltage higher than the gate voltage is applied to its source or drain, a depletion layer at the surface of the source or drain overlapping with the gate electrode expands. The phenomenon of electrons tunneling from the valence band to the conduction band, or what is called a band-to-band tunneling phenomenon, has occurred, and at the surface, electrons and holes are generated. Then, as the electrons move to the drain and the holes move to the substrate, thus, a substrate current develops.
In a conventional device in FIGS. 7 and 8, a thin oxide film 54 is formed on the entire surface of the channel region of a data storage MOS transistor MT.
As shown in FIG. 9, when a high potential is applied to the n-type region (drain region) of the data storage MOS transistor MT in a write operation, a depletion layer at the surface of the n-type region (drain region) 52 overlapping with a floating-gate electrode 58 expands, allowing a substrate current Is to flow through band-to-band tunneling.
On the other hand, with the conventional device of FIGS. 1 and 2, as shown in FIG. 10, the gate oxide film 23 of the data storage MOS transistor MT is as thick as several tens nm, and one end of the n-type region (drain region) of the data storage MOS transistor MT is under the thick gate oxide film 23.
This prevents the depletion layer at the surface at the end of the n-type region (drain region) 13 from expanding further. Because the depletion layer at the surface acts as a potential barrier, the holes generated at the surface at the end of the n-type region 13 do not move to the substrate, and a substrate current due to band-to-band tunneling does not flow.
In the conventional device of FIGS. 4 and 5, a substrate current will not develop because of similar reasons.
In a nonvolatile semiconductor memory device which electrically write and erase data, high potentials necessary for a write operation and an erase operation are generated at the step-up circuit in the LSI, in some cases.
With the device of FIGS. 7 and 8, since a large substrate current develops during a write operation, it is difficult to cause the step-up circuit in the LSI to supply a high potential (a write current). Especially, at the time of a page rewrite operation in which data should be written into many memory cells. The writing of data may not be carried out.
A substrate current during a write operation increases the power consumption in the LSI. Therefore, in the case of an LSI required to be less power-consuming, such as a battery-powered LSI, the generation of substrate current is not desirable. That is, the conventional device of FIGS. 7 and 8 has the following disadvantage: although the cell area can be made very small, a substrate current flows due to band-to-band tunneling in a write operation, thus preventing a high potential from being generated within the LSI, with the result that a less power-consuming operation cannot be achieved.
As described above, the conventional nonvolatile semiconductor memory devices have disadvantages in that when they are designed to make smaller the drawn current during a write operation, the area of the memory cell becomes larger, and in that, conversely, when they are designed to make the area of the memory cell much smaller, the drawn current during a write operation becomes larger.